Intel goes 32nm

Not just for AMD any more...

Intel is starting to talk about 32nm, and it is as it should be, with one big exception. While everyone focuses on the rather pedestrian bleeding edge headline, they missed the part about immersion.

The main thing that everyone seems to be interested in is that Intel made an announcement about 32nm chips. They scaled features linearly by .7x, so area goes down by about 50 per cent. Transistor gate pitch is 112.5nm, the smallest reported to date for any 32nm technology.

They demoed this as early as September 2007 with a 291 Mb SRAM chip. It has a .171µm^2 cell size, and used more than 1.9 Billion transistors. To put that in perspective, it is almost one transistor for every $350 given to banks in the recent 'bailout'. Talk about big numbers...

The new transistors use a second generation high-K + metal gate structure, the first generation was on 45nm.

This means chips made on the process should have low power use and leakage will be far less of a problem than without. If you are thinking evolutionary, you would be right so far. The big bang was quite well hidden though. If you read the papers that they are going to present at IEDM, you will see that they have a special feature, immersion. The paper, "A 32nm Logic Technology Featuring Second Generation High-k + Metal Gate Transistors, Enhanced Channel Strain and 0.171um2 SRAM Cell Size in a 291Mb Array" has it in the abstract. It says, "193nm immersion lithography for critical patterning layers". That more than anything is the big bang from a technology point of view.

The next step is EUV for 22nm. We are not supposed to have figured that out yet, but since they are openly posting jobs for EUV mask makers at the 22nm node, we kind of put 2 and 2 together to get 22. Cymer says they will be there in time, so things are going to get interesting and quite expensive in 3 years time.

Source http://www.atomicmpc.com.au/News/130799,intel-goes-32nm.aspx